The copper (Cu) damascene method has become mainstream in the manufacture of copper interconnects in microminiaturized integrated circuits (IC). Currently, chemical mechanical polishing (CMP) of the copper layers includes an oxide buffing step to reduce dishing and erosion of the copper interconnects. Dishing causes reduced yields, unreliability and unacceptable performance. The deleterious effects of dished copper interconnects accumulate interconnect level by interconnect level. However, the oxide buffing step worsens the resistance (Rs) uniformity of the formed Cu interconnects and lines formed.
U.S. Pat. No. 5,818,110 to Cronin discloses an integrated circuit chip wiring structure, especially dynamic random access memory (DRAM), having crossover and contact capability without an interlock via layer, and a method of making same. This method permits selective exposure of the metal lines in a first insulative layer so that an electrical connection is made with the metal wire of the second insulative layer in the exposed areas. A multi-damascene approach is used to wire the first, thin metallization layer, then providing the second, thick metallization layer with first regions for metal wire and second regions for metal wire that are thinner than the first regions. A conformal layer coating is deposited that fills the second regions but not the first, wider regions. When an etch is then performed, the conformal layer in the wider first regions are completely etched away permitting exposure of the underlying thin metallization layer and formation of electrical connections in those first regions.
U.S. Pat. No. 5,244,534 to Yu et al. describes a two step chemical mechanical polishing (CMP), or planarization, technique in the formation of a planar metal plug flush with, or a convex metal plug that slightly protrudes from, an insulation layer in integrated circuit chips. The metal plug is preferably comprised of tungsten (W). Tungsten is deposited on a trenched insulation layer and the first CMP process that is selective to the W is used to remove W from the surface of the insulation layer and leaving slightly recessed W plugs within the trenches, or contact holes. The second CMP process is selective to the insulation layer and only slightly affects the W plugs to leave either: convex protruding W plugs or polished planar W plugs in the trenches.
U.S. Pat. No. 5,676,587 to Landers et al. describes a method of removing the tungsten (W) or copper (Cu) layer and a Ti/TiN (titanium/titanium nitride) or Ta/TaN (tantalum/tantalum nitride) liner film from the surface of an oxide layer which does not require an oxide touch-up step to essentially replanarize the surface of the oxide. The method entails removing the first film with a first removal process and stopping the removal before the first film is completely removed. The remaining first film is removed using a second removal process that is selective to the first film.
U.S. Pat. No. 5,356,513 to Burke et al. describes a method of producing a substantially planar surface overlying features of a semiconductor structure by the use of forming alternating layers of a hard polishing material and a soft alternating layer over the features of the semiconductor structure. The alternating hard and soft layers are then polished to form a substantially planar surface over the features.
U.S. Pat. No. 5,821,168 to Jain describes a process for forming a semiconductor device in which an insulating layer is nitrided and then covered by a thin adhesion layer before depositing a composite copper layer. This process eliminates the need for a separate diffusion barrier since a portion of the insulating layer is converted to form a diffusion barrier film and the adhesion layer reacts with the interconnect material resulting in strong adhesion between the composite copper layer and the diffusion barrier film formed on the insulating layer. After a copper seed layer is deposited by physical vapor deposition over the adhesion layer using a collimated sputtering chamber, the substrate is taken to an electroplating system where 6,000-15,000 xc3x85 of copper is plated over the copper seed layer forming a composite copper layer with the copper seed layer indistinguishable from the plated copper layer. CMP then removes the composite copper layer overlying the uppermost surface of the insulating layer.
Accordingly, it is an object of the present invention to provide an improved method of forming planar copper interconnects.
Another object of the present invention is to provide an improved method of forming planarized copper interconnects having increased resistance (Rs) uniformity and good planarity of the formed Cu interconnects and lines.
A further object of the present invention is to provide an improved method of forming planar copper interconnects by use of a sacrificial layer.
Yet another object of the present invention is to provide an improved method of forming planar copper interconnects by use of a first Cu layer selective CMP followed by a second sacrificial layer selective oxide buffing step.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure is provided. A low K dielectric layer is formed over the semiconductor structure. A sacrificial oxide layer is formed over the low K dielectric layer. The sacrificial layer and low K dielectric layer are damascene patterned to form a trench within the sacrificial oxide layer and low K dielectric layer. A barrier layer is formed over the sacrificial oxide layer, lining the trench side walls and bottom. Metal is deposited on the barrier layer to form a metal layer filling the lined trench and blanket filling the sacrificial-oxide-layer-covered low K dielectric layer. The metal layer and the barrier layer are planarized, exposing the upper surface of the sacrificial layer. The sacrificial layer is then removed by oxide buffing to form a planarized metal interconnect.